library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity Logic_GateMDR is
   port(Data_Size: in bit; -- word/byte
        MAR_out,MDR: in unsigned(15 downto 0);
        GateMDR: out unsigned(15 downto 0));
end Logic_GateMDR;

architecture Code of Logic_GateMDR is
--signal count: integer range 0 to 8:=to_integer(Data_Size);
--constant count: integer range 0 to 8:=to_integer(Data_Size);    
begin
--count <= to_integer(Data_Size);
process (MDR,Data_Size,MAR_out)
  begin
    if Data_Size = '1' then
        GateMDR <= MDR;
    elsif Data_Size = '0' then
        if MAR_out(0) = '0' then    --even byte
            GateMDR <= MDR and "0000000011111111";
            if MDR(7) = '1' then 
                GateMDR <= MDR or "1111111100000000";
            end if;
        elsif MAR_out(0) = '1' then   --odd byte (high)
            if MDR(15) = '1' then 
            GateMDR <= ((MDR srl 8) or "1111111100000000");   --"11111111" & (Mem_bus srl 8);
            else GateMDR <= ((MDR srl 8) and "0000000011111111");  -- "00000000" & (Mem_bus srl 8);
            end if;
        end if;
    end if;
  
  end process;   

end Code;
